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300 mhz, 32 16 buffered analog crosspoint switch adv3202/ADV3203 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. features large, 32 16, nonblocking switch array g = +1 (adv3202) or g = +2 (ADV3203) operation 32 32 pin-compatible version available (adv3200/adv3201) single +5 v, dual 2.5 v, or dual 3.3 v supply (g = +2) serial programming of switch array 2:1 osd insertion mux per output input sync-tip clamp high impedance output disable allows connection of multiple devices with minimal output bus load excellent video performance 60 mhz 0.1 db gain flatness 0.1% differential gain error (r l = 150 ) 0.1 differential phase error (r l = 150 ) excellent ac performance bandwidth: >300 mhz slew rate: >400 v/s low power: 1 w low all hostile crosstalk: ?48 db @ 5 mhz reset pin allows disabling of all outputs connected through a capacitor to ground, provides power-on reset capability 176-lead exposed pad lqfp package (24 mm 24 mm) applications cctv surveillance routing of high speed signals, including composite video (ntsc, pal, s, secam) rgb and component video routing compressed video (mpeg, wavelet) video conferencing functional block diagram v v neg dgnd dvcc pos data out enable/ disable 193-bit shift register parallel latch 16 5:32 decoders adv3202 (ADV3203) output buffer g = +1 (g = +2) enable/ bypass 16 97 96 512 sync-tip clamp switch matrix osd mux 16 outputs 32 inputs . . . . . . . . . . . . 16 16 reference clk data in vclamp vref osd inputs osd switches 07526- 001 update cs reset 96 figure 1. general description the adv3202/ADV3203 are 32 16 analog crosspoint switch matrices. they feature a selectable sync-tip clamp input for ac-coupled applications and a 2:1 on-screen display (osd) insertion mux. with ?48 db of crosstalk and ?80 db isolation at 5 mhz, the adv3202/ADV3203 are useful in many high density routing applications. the 0.1 db flatness out to 60 mhz makes the adv3202/ADV3203 ideal for both composite and component video switching. the 16 independent output buffers of the adv3202/ADV3203 can be placed into a high impedance state for paralleling cross- point outputs so that off-channels present minimal loading to an output bus if building a larger array. the adv3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. a single +5 v supply, dual 2.5 v supplies, or dual 3.3 v supplies (g = +2) can be used while consuming only 195 ma of idle current with all outputs enabled. the channel switching is performed via a double buffered, serial digital control that can accommodate daisy chaining of several devices. the adv3202/ADV3203 are packaged in a 176-lead exposed pad lqfp package (24 mm 24 mm) and are available over the extended industrial temperature range of ?40c to +85c.
adv3202/ADV3203 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? osd disabled ................................................................................ 3 ? osd enabled ................................................................................. 4 ? timing characteristics (serial mode) ....................................... 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? power dissipation..........................................................................6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? truth table and logic diagram ............................................... 10 ? typical performance characteristics ........................................... 11 ? theory of operation ...................................................................... 14 ? applications information .............................................................. 16 ? programming .............................................................................. 16 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 17 ? revision history 10/08revision 0: initial version
adv3202/ADV3203 rev. 0 | page 3 of 20 specifications osd disabled v s = 2.5 v (adv3202), v s = 3.3 v (ADV3203) at t a = 25c, g = +1 (adv3202), g = +2 (ADV3203), r l = 150 , all configurations, unless otherwise noted. table 1. parameter conditions adv3202/ADV3203 unit min typ max dynamic performance ?3 db bandwidth 200 mv p-p 300 mhz 2 v p-p 120 mhz gain flatness 0.1 db, 200 mv p-p 60 mhz 0.1 db, 2 v p-p 40 mhz settling time 1% , 2 v step 6 ns slew rate 2 v step, peak 400 v/s noise/distortion performance differential gain error ntsc or pal 0.06/0.1 % differential phase error ntsc or pal 0.06/0.03 degrees crosstalk, all hostile, rti f = 5 mhz, r l = 150 r l = 1 k ?48 ?65 db db f = 100 mhz, r l = 150 r l = 1 k ?23 ?30 db db off isolation, input-to-output f = 5 mhz, one channel ?80 db input voltage noise 0.1 mhz to 50 mhz 25/22 nv/hz dc performance gain error broadcast mode, no load 0.5 1.75/2.2 % broadcast mode 0.5 2.2/2.7 % gain matching no load, channel-to-channel 0.5/0.8 2.8 % channel-to-channel 0.5/0.8 3.4 % output characteristics output impedance dc, enabled 0.15 dc, disabled 900/3.2 1000/4 k output capacitance disabled 3.7 pf output voltage range adv3202 ADV3203 ADV3203, no output load ?1.1 to +1.1 ?1.5 to +1.5 ?1.5 to +1.5 ?1.2 to +1.2 ?1.6 to +2.0 ?2.0 to +2.0 v v v input characteristics input offset voltage 5 30 mv input voltage range adv3202 ADV3203 ADV3203, no output load ?1.1 to +1.1 ?0.75 to +0.75 ?0.75 to +0.75 ?1.2 to +1.2 ?0.8 to +1.0 ?1.0 to +1.0 v v v input capacitance 3 pf input resistance 1 4 m input bias current sync-tip clamp enabled, v in = vclamp + 0.1 v 0.1 3 12 a sync-tip clamp enabled, v in = vclamp ? 0.1 v ?2.9 ?1 ?0.25 ma sync-tip clamp disabled ?10 ?3 a switching characteristics enable on time 50% update to 1% settling 50 ns switching time, 2 v step 50% up date to 1% settling 40 ns switching transient (glitch) in00 to in31, rti 300 mv p-p
adv3202/ADV3203 rev. 0 | page 4 of 20 parameter conditions adv3202/ADV3203 unit min typ max power supplies supply current v pos or v neg , outputs enabled, no load 195/200 220/235 ma v pos or v neg , outputs disabled 120/130 155/165 ma d vcc 2.5 3.5 ma supply voltage range v pos ? v neg 5 10%/ 6.6 10% v psr v neg , v pos , f = 1 mhz ?50/?45 db operating temperature range temperature range operating (still air) ?40 to +85 c ja operating (still air) 16 c/w osd enabled v s = 2.5 v (adv3202), v s = 3.3 v (ADV3203) at t a = 25c, g = +1 (adv3202), g = +2 (ADV3203), r l = 150 , all configurations, unless otherwise noted. table 2. parameter conditions adv3202/ADV3203 unit min typ max osd dynamic performance ?3 db bandwidth 200 mv p-p 170/150 mhz 2 v p-p 135/130 mhz gain flatness 0.1 db, 200 mv p-p 35 mhz 0.1 db, 2 v p-p 35 mhz settling time 1%, 2 v step 6 ns slew rate 2 v step, peak 400 v/s osd noise/distortion performance differential gain error ntsc or pal 0.12/0.35 % differential phase error ntsc or pal 0.06/0.04 degrees input voltage noise 0.5 mhz to 50 mhz 27/25 nv/hz osd dc performance gain error no load 0.1 2.3/2.2 % 0.1 2.7 % osd input characteristics input bias current sync-tip clamp disabled ?10 ?4 a osd switching characteristics osd switch delay, 2 v step 50% osd switch to 1% settling 20 ns osd switching transient (glitch) 15/40 mv p-p
adv3202/ADV3203 rev. 0 | page 5 of 20 timing characteristics (serial mode) specifications subject to change without notice. table 3. limit parameter symbol min typ max unit serial data setup time t 1 40 ns clk pulse width t 2 50 ns serial data hold time t 3 50 ns clk pulse separation t 4 150 ns clk to update delay t 5 50 160 ns update pulse width t 6 40 ns clk to data out valid t 7 130 ns propagation delay, update to switch on or off 50 ns data load time, clk = 5 mhz, serial mode 38.6 s reset time 160 ns transfer data from serial register to parallel latches during low level out00 (d0) out15 (d5) clamp on/off 1 0 1 0 1 0 1 = latched 0 = transparent data out update data in clk cs t 1 t 3 t 7 t 5 t 6 load data into serial register on rising edge t 2 t 4 7526-002 0 figure 2. timing diagram, serial mode table 4. logic levels, dvcc = 3.3 v v ih v il v oh v ol i ih i il i oh i ol reset , cs , clk, data in, update , osds reset , cs , clk, data in, update , osds data out data out reset , cs , clk, data in, update , osds reset , cs , clk, data in, update , osds data out data out 2.5 v min 0.8 v max 2.7 v min 0.5 v max 0.5 a typ ?0.5 a typ 3 ma typ ?3 ma typ
adv3202/ADV3203 rev. 0 | page 6 of 20 absolute maximum ratings power dissipation table 5. parameter rating analog supply voltage (v pos ? v neg ) 7.5 v digital supply voltage (dvcc ? d gnd ) 6 v ground potential difference (v neg ? d gnd ) +0.5 v to C4 v maximum potential difference dvcc ? v neg 9.4 v disabled outputs adv3202 (|v osd ? v out |) <3 v ADV3203 (|v osd ?(v out +v ref )/2|) <3 v |v clamp ? v inxx | 6 v v ref input voltage adv3202 v pos C 3.5 v to v neg + 3.5 v ADV3203 v pos C 4 v to v neg + 4 v analog input voltage v neg to v pos digital input voltage dvcc output voltage (disabled analog output) (v pos ? 1 v) to (v neg + 1 v) output short-circuit duration momentary output short-circuit current 45 ma storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c the adv3202/ADV3203 are operated with 2.5 v, +5 v, or 3.3 v supplies and can drive loads down to 150 , resulting in a large range of possible power dissipations. for this reason, extra care must be taken while derating the operating conditions based on ambient temperature. packaged in a 176-lead exposed-pad lqfp, the adv3202/ ADV3203 junction-to-ambient thermal impedance ( ja ) is 16c/w. for long-term reliability, the maximum allowed junction temperature of the die should not exceed 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. figure 3 shows the range of allowed internal die power dissipations that meet these conditions over the ?40c to +85c ambient temperature range. when using figure 3 , do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors. 9 8 7 6 5 4 3 15 25 35 45 55 65 75 85 ambient temperature (c) maximum power (w) 07526-003 t j = 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 3. maximum die power dissipation vs. ambient temperature thermal resistance esd caution ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 6. thermal resistance package type ja unit 176-lead lqfp_ep 16 c/w
adv3202/ADV3203 rev. 0 | page 7 of 20 pin configuration and fu nction descriptions pin 1 1 dvcc 2 nc 3 4 clk 5 data in 6 data out 7 8 9 dgnd 10 in00 11 dgnd 12 in01 13 dgnd 14 in02 15 dgnd 16 in03 17 dgnd 18 in04 19 dgnd 20 in05 21 dgnd 22 in06 23 dgnd 24 in07 25 dgnd 26 in08 27 dgnd 28 in09 29 dgnd 30 in10 31 dgnd 32 in11 33 dgnd 34 in12 35 dgnd 36 in13 37 dgnd 38 in14 39 dgnd 40 in15 41 vneg 42 vref 43 vclamp 44 osd15 89 vneg 90 osd03 91 osd02 92 osd01 93 osd00 94 vpos 95 in31 96 osds15 97 in30 98 osds14 99 in29 100 osds13 101 in28 102 osds12 103 in27 104 osds11 105 in26 106 osds10 107 in25 108 osds09 109 in24 110 osds08 111 in23 112 osds07 113 in22 114 osds06 115 in21 116 osds05 117 in20 118 osds04 119 in19 120 osds03 121 in18 122 osds02 123 in17 124 osds01 125 in16 126 osds00 127 nc 128 nc 129 nc 130 nc 131 nc 132 vneg 133 nc 134 nc 135 nc 136 vpos 137 nc 138 vneg 139 nc 140 vpos 141 nc 142 vneg 143 nc 144 vpos 145 nc 146 vneg 147 nc 148 vpos 149 nc 150 vneg 151 nc 152 vpos 153 nc 154 vneg 155 nc 156 vpos 157 nc 158 vneg 159 nc 160 vpos 161 nc 162 vneg 163 nc 164 vpos 165 nc 166 vneg 167 nc 168 vpos 169 nc 170 nc 171 nc 172 nc 173 nc 174 nc 175 nc 176 dgnd 45 osd14 46 osd13 47 osd12 48 osd11 49 osd10 50 osd09 51 osd08 52 vpos 53 out15 54 vneg 55 out14 56 vpos 57 out13 58 vneg 59 out12 60 vpos 61 out11 62 vneg 63 out10 64 vpos 65 out09 66 vneg 67 out08 68 vpos 69 out07 70 vneg 71 out06 72 vpos 73 out05 74 vneg 75 out04 76 vpos 77 out03 78 vneg 79 out02 80 vpos 81 out01 82 vneg 83 out00 84 vpos 85 osd07 86 osd06 87 osd05 88 osd04 adv3202/ADV3203 top view (not to scale) reset 07526-004 update cs notes 1. nc = no connect 2. osds#: osd select for output # osd#: osd video input for output # 3. the exposed pad should be connected to analog ground. figure 4. pin configuration
adv3202/ADV3203 rev. 0 | page 8 of 20 table 7. pin function descriptions pin mnemonic description 1 dvcc digital positive power supply. 2 nc no connect. 3 reset control pin: 1 st and 2 nd rank reset. 4 clk control pin: serial data clock. 5 data in control pin: serial data in. 6 data out control pin: serial data out. 7 update control pin: second rank write strobe. 8 cs control pin: chip select. 9 dgnd digital negative power supply. 10 in00 input number 0. 11 dgnd digital negative power supply. 12 in01 input number 1. 13 dgnd digital negative power supply. 14 in02 input number 2. 15 dgnd digital negative power supply. 16 in03 input number 3. 17 dgnd digital negative power supply. 18 in04 input number 4. 19 dgnd digital negative power supply. 20 in05 input number 5. 21 dgnd digital negative power supply. 22 in06 input number 6. 23 dgnd digital negative power supply. 24 in07 input number 7. 25 dgnd digital negative power supply. 26 in08 input number 8. 27 dgnd digital negative power supply. 28 in09 input number 9. 29 dgnd digital negative power supply. 30 in10 input number 10. 31 dgnd digital negative power supply. 32 in11 input number 11. 33 dgnd digital negative power supply. 34 in12 input number 12. 35 dgnd digital negative power supply. 36 in13 input number 13. 37 dgnd digital negative power supply. 38 in14 input number 14. 39 dgnd digital negative power supply. 40 in15 input number 15. 41 vneg analog negative power supply. 42 vref reference voltage. see the theory of operation section for details. 43 vclamp sync-tip clamp voltage. see the theory of operation section for details. 44 osd15 osd input number 15. 45 osd14 osd input number 14. 46 osd13 osd input number 13. 47 osd12 osd input number 12. 48 osd11 osd input number 11. 49 osd10 osd input number 10. pin mnemonic description 50 osd09 osd input number 9. 51 osd08 osd input number 8. 52 vpos analog positive power supply. 53 out15 output number 15. 54 vneg analog negative power supply. 55 out14 output number 14. 56 vpos analog positive power supply. 57 out13 output number 13. 58 vneg analog negative power supply. 59 out12 output number 12. 60 vpos analog positive power supply. 61 out11 output number 11. 62 vneg analog negative power supply. 63 out10 output number 10. 64 vpos analog positive power supply. 65 out09 output number 9. 66 vneg analog negative power supply. 67 out08 output number 8. 68 vpos analog positive power supply. 69 out07 output number 7. 70 vneg analog negative power supply. 71 out06 output number 6. 72 vpos analog positive power supply. 73 out05 output number 5. 74 vneg analog negative power supply. 75 out04 output number 4. 76 vpos analog positive power supply. 77 out03 output number 3. 78 vneg analog negative power supply. 79 out02 output number 2. 80 vpos analog positive power supply. 81 out01 output number 1. 82 vneg analog negative power supply. 83 out00 output number 0. 84 vpos analog positive power supply. 85 osd07 osd input number 7. 86 osd06 osd input number 6. 87 osd05 osd input number 5. 88 osd04 osd input number 4. 89 vneg analog negative power supply. 90 osd03 osd input number 3. 91 osd02 osd input number 2. 92 osd01 osd input number 1. 93 osd00 osd input number 0. 94 vpos analog positive power supply. 95 in31 input number 31. 96 osds15 control pin: osd select number 15. 97 in30 input number 30. 98 osds14 control pin: osd select number 14. 99 in29 input number 29. 100 osds13 control pin: osd select number 13.
adv3202/ADV3203 rev. 0 | page 9 of 20 pin mnemonic description 101 in28 input number 28. 102 osds12 control pin: osd select number 12. 103 in27 input number 27. 104 osds11 control pin: osd select number 11. 105 in26 input number 26. 106 osds10 control pin: osd select number 10. 107 in25 input number 25. 108 osds09 control pin: osd select number 9. 109 in24 input number 24. 110 osds08 control pin: osd select number 8. 111 in23 input number 23. 112 osds07 control pin: osd select number 7. 113 in22 input number 22. 114 osds06 control pin: osd select number 6. 115 in21 input number 21. 116 osds05 control pin: osd select number 5. 117 in20 input number 20. 118 osds04 control pin: osd select number 4. 119 in19 input number 19. 120 osds03 control pin: osd select number 3. 121 in18 input number 18. 122 osds02 control pin: osd select number 2. 123 in17 input number 17. 124 osds01 control pin: osd select number 1. 125 in16 input number 16. 126 osds00 control pin: osd select number 0. 127 nc no connect. 128 nc no connect. 129 nc no connect. 130 nc no connect. 131 nc no connect. 132 vneg analog negative power supply. 133 nc no connect. 134 nc no connect. 135 nc no connect. 136 vpos analog positive power supply. 137 nc no connect. 138 vneg analog negative power supply. 139 nc no connect. pin mnemonic description 140 vpos analog positive power supply. 141 nc no connect. 142 vneg analog negative power supply. 143 nc no connect. 144 vpos analog positive power supply. 145 nc no connect. 146 vneg analog negative power supply. 147 nc no connect. 148 vpos analog positive power supply. 149 nc no connect. 150 vneg analog negative power supply. 151 nc no connect. 152 vpos analog positive power supply. 153 nc no connect. 154 vneg analog negative power supply. 155 nc no connect. 156 vpos analog positive power supply. 157 nc no connect. 158 vneg analog negative power supply. 159 nc no connect. 160 vpos analog positive power supply. 161 nc no connect. 162 vneg analog negative power supply. 163 nc no connect. 164 vpos analog positive power supply. 165 nc no connect. 166 vneg analog negative power supply. 167 nc no connect. 168 vpos analog positive power supply. 169 nc no connect. 170 nc no connect. 171 nc no connect. 172 nc no connect. 173 nc no connect. 174 nc no connect. 175 nc no connect. 176 dgnd digital negative power supply. epad (exposed pad) connect to analog ground.
adv3202/ADV3203 rev. 0 | page 10 of 20 truth table and logic diagram table 8. operation truth table cs update clk data input data output reset operation/comment x x x x x 0 asynchronous reset. all outputs are disabled; the 193-bit shift register is reset to all 0s. 0 1 data i 1 data i-193 1 the data on the serial data in line is loaded into the serial register. the first bit clocked into the serial register appears at data out 193 clock cycles later. 0 0 x x x 1 switch matrix update. data in th e 193-bit shift register transfers into the parallel latches that control the switch array and sync- tip clamps. 1 x x x x 1 chip is not sele cted. no change in logic. 1 data i : serial data.
adv3202/ADV3203 rev. 0 | page 11 of ?12 1 10 100 1k frequency (mhz) 07526-005 20 typical performance characteristics v s = 2.5 v (adv3202), v s = 3.3 v (ADV3203) at t a = 25c, r l = 150 . 2 0 ?2 ?4 ?6 ?8 ?10 gain (db) inxx osdxx figure 5. adv3202 small signal frequency response, 200 mv p-p 2 0 ?2 ?4 ?6 ?8 ?10 gain (db) 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 0 2 4 6 8 101214 161820 time (ns) v out (v) 07526-008 inxx osdxx figure 8. adv3202 large signal pulse response, 2 v p-p 600 400 200 0 ?200 ?400 ?600 02468101214161820 time (ns) 07526-009 ?12 1 10 100 1k frequency (mhz) 07526-006 inxx osdxx figure 6. adv3202 large sign al frequency response, 2 v p-p 0.12 0.08 0.04 0 ?0.04 ?0.08 v out (v) rising edge ?0.12 0 2 4 6 8 101214 161820 time (ns) 07526-007 inxx osdxx figure 7. adv3202 small sign al pulse response, 200 mv p-p falling edge dv/dt (v/s) figure 9. adv3202 slew rate 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.7 ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.7 input dc offset (v) differential gain (%) 07526-010 figure 10. adv3202 differential gain, carrier frequency = 3.58 mhz, subcarrier amplitude = 300 mv p-p
adv3202/ADV3203 rev. 0 | page 12 of 20 0.010 0.005 0 ?0.005 ?0.010 ?0.015 differential phase (degrees) 0.12 0.08 0.04 0 ?0.04 ?0.08 ?0.12 0 2 4 6 8 101214 161820 time (ns) v out (v) 07526-014 ?0.020 ?0.7 ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.7 input dc offset (v) 07526-011 figure 11. adv3202 differential phase, carrier frequency = 3.58 mhz, subcarrier amplitude = 300 mv p-p 8 6 4 2 0 ?2 ?4 gain (db) osdxx inxx figure 14. ADV3203 small signal pulse response, 200 mv p-p 1.2 0.8 0.4 0 ?0.4 ?0.8 ?1.2 0 2 4 6 8 101214 161820 time (ns) v out (v) 07526-015 ?6 1 10 100 1k frequency (mhz) 526-012 07 osdxx inxx figure 12. ADV3203 sm all signal frequency response, 200 mv p-p 8 6 4 2 0 ?2 ?4 gain (db) osdxx inxx 600 400 200 0 ?200 ?400 ?600 0 2 4 6 8 101214 161820 dv/dt (v/s) 6-016 figure 15. ADV3203 large signal pulse response, 2 v p-p time (ns) 0752 ?6 1 10 100 1k frequency (mhz) 07526-013 osdxx inxx figure 13. ADV3203 large sign al frequency response, 2 v p-p rising edge falling edge figure 16. ADV3203 slew rate
adv3202/ADV3203 rev. 0 | page 13 of 20 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.7 ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.7 differential gain (%) 6-017 input dc offset (v) 0752 figure 17. ADV3203 differential gain, carrier frequency = 3.58 mhz, subcarrier amplitude = 300 mv p-p 0.05 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 differential phase (degrees) ?0.04 ?0.05 ?0.7 ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.7 input dc offset (v) 07526-018 figure 18. ADV3203 differential phase, carrier frequency = 3.58 mhz, subcarrier amplitude = 300 mv p-p
adv3202/ADV3203 rev. 0 | page 14 of 20 theory of operation the adv3202/ADV3203 are single-ended crosspoint arrays with 16 outputs, each of which can be connected to any one of 32 inputs.the 32 switchable input stages are connected to each output buffer to form 32-to-1 multiplexers. there are 16 of these multiplexers, each with its inputs wired in parallel, for a total array of 512 stages forming a multicast-capable crosspoint switch. in addition to connecting to any of the nominal inputs (inxx), each output can also be connected to an associated osd input through an additional 2-to-1 multiplexer at each output. this 2-to-1 multiplexer switches between the output of the 32- to-1 multiplexer and the osd input. each input to the adv3202/ADV3203 is buffered by a receiver. the purpose of this receiver is to provide overvoltage protection for the input stages by limiting signal swing. in the adv3202, the output of the receiver is limited to 1.2 v about vref, while in the ADV3203, the signal swing is limited to 1.2 v about midsupply. this receiver is configured as a voltage feedback unity-gain amplifier. excess loop gain bandwidth product reduces the effect of the closed-loop gain on the bandwidth of the device. in addition to a receiver, each input also has a sync-tip clamp for use in ac-coupled applications. this clamp is either enabled or disabled according to the 193 rd serial data bit. when enabled, the clamp forces the lowest video voltage to the voltage on the vclamp pin. the vclamp pin is common for the entire chip and needs to be driven with a low impedance to avoid crosstalk. x1 out00 v pos vneg from input stages vpos vneg osd00 osds00 9 07526-01 figure 19. conceptual diagram of single output channel, g = +1 (adv3202) decoding logic for each output selects one (or none) of the input stages to drive the output stage. the enabled input stage drives the output stage, which is configured as a unity-gain amplifier in the adv3202 (see figure 19 ). in the ADV3203, an internal resistive feedback network and reference buffer provide for a total output stage gain of +2 (see figure 20 ). the input voltage to the reference buffer is the vref pin. this voltage is common for the entire chip and needs to be driven with a low impedance to avoid crosstalk. out00 x1 v pos vneg from input stages vpos vneg vref vpos vneg osd00 osds00 2k? 2k? 20 07526-0 figure 20. conceptual diagram of single output channel, g = +2 (ADV3203) 07526-021 in00 v pos v pos vneg v clamp 5a to input receiver off-chip capacitor figure 21. conceptual diagram of sync-tip clamp in an ac-coupled application the output stage of the adv3202/ADV3203 is designed for low differential gain and phase error when driving composite video signals. it also provides slew current for fast pulse response when driving component video signals. the outputs of the adv3202/ADV3203 can be disabled to minimize on-chip power dissipation. when disabled, a series of internal amplifiers drive internal nodes such that a wideband high impedance is presented at the disabled output, even while the output bus is under large signal swings. (in the ADV3203, there is 4 k of resistance terminated to the vref voltage by the reference buffer). this high impedance allows multiple ics to be bussed together without additional buffering. care must be taken to reduce output capacitance, which results in more overshoot and frequency domain peaking. in addition, when the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the adv3202/ADV3203 to keep these internal amplifiers in their linear range of operation. applying excess voltage to the disabled outputs can cause damage to the adv3202/ADV3203 and should be avoided (see the absolute maximum ratings section for guidelines).
adv3202/ADV3203 rev. 0 | page 15 of 20 the internal connection of the adv3202/ADV3203 is controlled by a ttl-compatible logic interface. serial loading into a first rank of latches preprograms each output. a global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. a serial out pin allows devices to be daisy chained together for single pin programming of multiple ics. a power-on reset pin is available to prevent bus conflicts by disabling all outputs. the adv3202 can operate on a single +5 v supply, powering both the signal path (with the vpos/vneg supply pins) and the control logic interface (with the vdd/dgnd supply pins). however, to easily interface to ground referenced video signals, split supply operation is possible with 2.5 v. (the ADV3203 is intended to operate on 3.3 v.) in the case of split supplies, a flexible logic interface allows the control logic supplies (vdd/dgnd) to be run off +3.3 v/0 v to +5 v/0 v while the core remains on split supplies.
adv3202/ADV3203 rev. 0 | page 16 of 20 applications information programming the adv3202/ADV3203 are programmed serially through a 193-bit serial word that updates the matrix and the state of the sync-tip clamps each time the part is programmed. serial programming description the serial programming mode uses the clk, data in, update , and cs device pins. the first step is to assert a low on cs to select the device for programming. the update signal should be high during the time that data is shifted into the serial port of the device. although the data still shifts in when update is low, the transparent, asynchronous latches allow the shifting data to reach the matrix. this causes the matrix to try to update to every intermediate state as defined by the shifting data. the data at data in is clocked in at every rising edge of clk. a total of 193 bits must be shifted in to complete the program- ming. for each of the 16 outputs, there are five bits (d0 to d4) that determine the source of its input followed by one bit (d5) that determines the enabled state of the output. if d5 is low (output disabled), the five associated bits (d0 to d4) do not matter because no input is switched to that output. these comprise the first 96 bits of data in. the remaining 96 bits of data in should be set to zero. if a string of 96 zeros is not suffixed to the first 96 bits of data in, a certain test mode is employed that can cause the device to draw up to 30% more current. the last bit, bit 193, is used to enable or disable the sync-tip clamps. if bit 193 is low, the sync-tip clamps are disabled; otherwise, they are enabled. the sync-tip clamp bit is shifted in first, followed by the most significant output address data (out15). the enable bit (d5) is shifted in first, followed by the input address (d4 to d0) entered sequentially with d4 first and d0 last. each remaining output is programmed sequentially, until the least significant output address data is shifted in. at this point, update can be taken low, which causes the programming of the device according to the data that was just shifted in. the update latches are asynchronous and when update is low, they are transparent. if more than one adv3202/ADV3203 device is to be serially programmed in a system, the data out signal from one device can be connected to the data in of the next device to form a serial chain. all of the clk and update pins should be connected in parallel and operated as described previously. the serial data is input to the data in pin of the first device of the chain, and it ripples through to the last. therefore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the programming sequence is 193 bits times the number of devices in the chain. reset when powering up the adv3200/adv3201, it is often useful to have the outputs come up in the disabled state. the reset pin, when taken low, causes all outputs to be disabled. after power-up, the update pin should be driven high prior to raising reset . because the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix may enter unknown states. to prevent this, do not apply a logic low signal to update initially after power-up. the shift register should first be loaded with data and update then taken low to program the device. the reset pin has a 25 k pull-up resistor to dvcc that can be used to create a simple power-on reset circuit. a capacitor from reset to ground holds reset low for some time while the rest of the device stabilizes. the low condition causes all the outputs to be disabled. the capacitor then charges through the pull-up resistor to the high state, thus allowing full programming capability of the device. the cs pin has a 25 k pull-down resistor to ground.
adv3202/ADV3203 rev. 0 | page 17 of 20 compliant to jedec standards ms-026-bga-hd 081808-a outline dimensions 0.15 0.10 0.05 0.08 coplanarity 0.20 0.15 0.09 1.45 1.40 1.35 7 3.5 0 view a rotated 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc 24.10 24.00 sq 23.90 26.20 26.00 sq 25.80 lead pitch top view (pins down) bottom view (pins up) exposed pad 1 44 1 44 45 89 88 45 88 132 89 132 176 133 176 133 pin 1 1.60 max 1.00 ref seating plane view a 7.80 ref 21.50 ref for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 22. 176-lead low profile quad flat package, exposed pad [lqfp_ep] (sw-176-1) dimensions shown in millimeters ordering guide model temperature range packag e description package option adv3202aswz 1 ?40c to +85c 176-lead low profile quad flat package, exposed pad [lqfp_ep] sw-176-1 ADV3203aswz 1 ?40c to +85c 176-lead low profile quad flat package, exposed pad [lqfp_ep] sw-176-1 1 z = rohs compliant part.
adv3202/ADV3203 rev. 0 | page 18 of 20 notes
adv3202/ADV3203 rev. 0 | page 19 of 20 notes
adv3202/ADV3203 rev. 0 | page 20 of 20 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07526-0-10/08(0)

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